Hi all,
I want try to a different approach on signaling the junctions. Therefore I'm in need of a pre-signal, that shows GREEN when the block behind is occupied, negating the signal (NOT). A normal pre-signal works as OR-gate, showing green when at least one track is free. An AND gate can be designed by connecting all the tracks after the exit-signal. For complex signaling, such as XOR, NAND and NOR i need the one that inverts the signal.
Imagine: I have a multiple track Mainline (4 for each direction). On my junctions from the sideline to the mainline I want to just connect the most outer line, which makes construction much easier. To give trains on the sideline the possibilty to join the mainline quite effective, it is necessary, that the outer most track is used as less as possible.
I want to force everey train on this track to switch if possible, so that the outer track is free most of the time. This approach isn't that new at all, but very hard to realize at the moment. With such a new signal, it could be versy easy to force trains to switch the track.
Greetings
Logical Gates
Moderator: OpenTTD Developers
Re: Logical Gates
Topic has been discussed, and solutions have been implemented.
Try the search button at the top.
Try the search button at the top.
Re: Logical Gates
Not exactly what you want but you can program the signals with this to do as you desire and more:
http://www.tt-forums.net/viewtopic.php? ... 0&stsart=0
http://www.tt-forums.net/viewtopic.php? ... 0&stsart=0
Re: Logical Gates
thank you very much, lawton. This surely will help me.
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Re: Logical Gates
I had similar idea, programmable signals are quite cool, but everything I need is "NAND signal", because with NAND you can do really everything. Programmable signals are too much clicking every time again, create NOT, AND or OR gate with NAND si really easy and clear...
Few months ago I did quite complex Main line joiner and its really annoying to do AND and NOT gates using trains and presignals... And you need to do some fail-safe improvements due to latency of trains :/ I want NAND signal too much
Few months ago I did quite complex Main line joiner and its really annoying to do AND and NOT gates using trains and presignals... And you need to do some fail-safe improvements due to latency of trains :/ I want NAND signal too much

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