Logic with logic trains

[mfb]

When I found Osai's blog entry about logic trains and Igloo's train counter, I tried to combine both. Unfortunately, the logic trains can get stuck in wrong positions - and with a lot of gates (like for the train counter), it happens quite frequently.
Using the end of tracks, I found gates without that problem. As a side effect, they are smaller, too.


Trains don't have any orders. red=1, green=0



Even if a train can move along the full track (all inputs green), it will always be at one end, giving the right output. Don't try this with regular trains, it won't work .

Reaction time:
With 22 NOT-gates in a row, a small delay (~1 tile for a maglev1-train) is visible.
16 OR-gates in a row (e.g. in a 16bit ripple carry adder) don't generate any delay.

It's possible to create very small logic elements with them:
4 full adders (some gates are bent to fit in)
multiplexer design just with AND and NOT. only one of eight 16bit-inputs is completed.
(1bit register (the new value is stored before the old value gets deleted))


Is it possible to copy trains (without orders) with the copy&paste-patch? I don't know how I can use it... but it should be possible to create a nice ALU or even a CPU with it.


Edit: Changed image format to .png

[XeryusTC]

Just a small comment to make your screenshots a bit easier to understand: don't use JPEG use PNG, you can even select it as a format from the OpenTTD options menu. That way it is way easier to recognise the type of signal etc as that kind of information doesn't get lost in compression. And when you do add those blocks to clarify what kind of signal it is don't make them square as there is a distinct directions of the sign on the entry and combo signals.

Oh, I forgot to add that your NOT gate might get some quite decent testing on the #openttdcoop Public Server (see signature for links) as it will run a logic heavy game and this gate seems like it will be faster and more efficient both space and needed trains wise. We'll be seeing some results in a few days I suspect.

[avdg]

It looks like a not fully functional working not gate, because there is a flaw when the input is green that the output 'flickers' (train is moving in and out the detected zone). However, it still doesn't mean it is a bad solution, in fact, I'm sure there are situations we simply don't care about its drawback.

But as XerytusTC already said, join the #OpenTTDCoop server. Its a great place for experiments and improvements and you are bang on time if you do it now, with our logic game .

[mfb]

Don't try this with regular trains, it won't work

OR and NOT are designed for the logic trains and work without any flaw with them.


Edit: Found a modified OR-gate for regular trains

[Radicalimero]

Is it possible to copy trains (without orders) with the copy&paste-patch?

the full adder itself is 12 * 11 tiles and i made it easy to add all train with only one depot

without trains.png

full adder with output register

(250.13 KiB) Downloaded 1 time

and i also made a full adder subtractor.

full adder subtractor.png

full adder subtractor

(279.93 KiB) Downloaded 1 time

[audigex]

How many Trainsistors do you think your OTTD CPU would have?

Sorry, I'll get my coat.

[mfb]

Nice idea with the single depot.


For a CPU, memory would need most of the gates.
~200-300 logic gates for an ALU, not counting AND.
But 100 words of memory (data+program) are 1600 memory-bits.


Some more stuff:

Useful for a balanced station entry, the trains split left->right->left->right-> ...

Balanced split with RS-latch

11-split.png (24.79 KiB) Viewed 11953 times

one example of handling 16bit-cables:

16bit-cables -> split or merge

16plus1-split.png (11.82 KiB) Viewed 11953 times

and an idea for an ALU. Supported: NOT, AND, OR, ADD, SUB
status bits are missing, but it's easy to build some lines for them.
Note that most of the space is necessary to connect the inputs to everything.

alu.png

ALU

(127.04 KiB) Downloaded 1 time

Edit: Completed the ALU

[DeletedUser6]

Could - if you have it - post the Copy and paste patch templates, or pm me them.

We could work together to create an O(penTTD)CPU or we name it a OpenCPU.

Matthew:out

[mfb]

Copy&paste-patch produced some errors about a sample.cat, I didn't manage to run it.

Many parts can be done quicker with it, but I don't know how many parts of a memory can be copied.


For NOT train injection, you can use something like this. Create trains, release all, demolish the western row (tiles with trains will stay), add the remaining part of the track and add signals.
At multiplexers, NOT(NOT(inputA) AND NOT(inputB) AND NOT(inputC) AND ...) requires more gates than (inputA OR input B OR input C OR) ..., but connecting all these OR-gates is a mess.



Edit 26.12.: Register

CPU Transport, 08-06-2096.png

(222.45 KiB) Downloaded 1 time

"write" is green (!) if the first word is written, write' is for the next word. Decoding is not included, as I don't have any specific processor design in mind (yet?).
readA sets output A to the value of the register, readB sets output B. readA' is for the next word and so on.

The trains to the left hold the ALU output for a while and enable to read and write the same register in one processor cycle.
One cycle consists of 4 steps. I'll call the left trains "X".

- hold register data, delete X. It's the longest part as calculations are done here.
- hold register data, store ALU output to X. Calculation is finished, the output is temporarily saved.
- hold X, delete word in the register (if necessary)
- hold X, write X to that register (if necessary)

I can count the clock cycles now .
ADD R1,R2 with fixed R2=1


Due to the nature of multiplexers, it's possible to calculate some additional ORs on the way with the ALU, for example "NOT A OR (A AND B)" (which is the same as A=>B).
It's even possible with registers, but I don't know if that is useful.

[agentw4b]

When I found Osai's blog entry about logic trains and Igloo's train counter, I tried to combine both. Unfortunately, the logic trains can get stuck in wrong positions - and with a lot of gates (like for the train counter), it happens quite frequently.
Using the end of tracks, I found gates without that problem. As a side effect, they are smaller, too.


Trains don't have any orders. red=1, green=0



Even if a train can move along the full track (all inputs green), it will always be at one end, giving the right output. Don't try this with regular trains, it won't work .

Reaction time:
With 22 NOT-gates in a row, a small delay (~1 tile for a maglev1-train) is visible.
16 OR-gates in a row (e.g. in a 16bit ripple carry adder) don't generate any delay.

It's possible to create very small logic elements with them:
4 full adders (some gates are bent to fit in)
multiplexer design just with AND and NOT. only one of eight 16bit-inputs is completed.
(1bit register (the new value is stored before the old value gets deleted))




Is it possible to copy trains (without orders) with the copy&paste-patch? I don't know how I can use it... but it should be possible to create a nice ALU or even a CPU with it.


Edit: Changed image format to .png

NOT gate does not work. The output signal flashes. I have it exactly as shown, but it does not work as you write it to work. What is wrong ? I have tested it with logic trains .

[Sylf]

NOT gate does not work. The output signal flashes. I have it exactly as shown, but it does not work as you write it to work. What is wrong ? I am tested it with logic trains .

It used to work in 2010. Things have changed somewhere I guess, that that design of NOT gate no longer works.
The NOT gate that was linked from the original post is not 100% accurate version - it works most of the time, but because of a branching with delay within the gate circuit, the NOT gate fails sometimes.
This NOT gate that was linked from that blog post has a footprint of 5x3 - it's rather big, but it works 100%.
The 3x3 NOT gate is still the tried-and-true design that never fails, although it wasn't quite as fast as mfb's 3x2 design. It works 100%, and this is probably the NOT gate that's used most often nowadays.

[kamnet]

Would it work better if using a NewGRF like Wired?

[Sylf]

Would it work better if using a NewGRF like Wired?

I don't think so, because that's just a special rail graphic that's made to look like simple signal wire - it doesn't contribute anything to the logic gates.

[agentw4b]

Would it work better if using a NewGRF like Wired?

I don't think so, because that's just a special rail graphic that's made to look like simple signal wire - it doesn't contribute anything to the logic gates.

The 3x3 NOT gate is well functional with Wired. "Block signal train " has zero costs.

But I wanted to use one train instead of two

[Sylf]

The 3x4 NOT gate uses 1 train, but like I said, it's not 100% fail safe. I've used it in various SRNW games, and it works well enough though.

[agentw4b]

But mfb's OR gate works well ( modified OR-gate )

[agentw4b]

I created a flip-flop without using logic gates. It uses instead the closest (fake) depot. The only problem is that when the train enters the (real) depot to evaluate how much percentage it is loaded, there must be a command on the waypoint or station to turn the train again from the depot (Bílý Úval Waypoint).

[agentw4b]

I created a flip-flop without using logic gates. It uses instead the closest (fake) depot. The only problem is that when the train enters the (real) depot to evaluate how much percentage it is loaded, there must be a command on the waypoint or station to turn the train again from the depot (Bílý Úval Waypoint).
]

Orders:

orders.png (6.61 KiB) Viewed 5417 times

[vrn]

I don't know what you are trying to accomplish here. A real flipflop splits trains equally in two or three directions, while the trains in your setup just choose any available path.

[agentw4b]

I don't know what you are trying to accomplish here. A real flipflop splits trains equally in two or three directions, while the trains in your setup just choose any available path.

Okay, it's not a flip-flop, but it's not a random path!

The train will go after each end of the circuit in a different direction, but the train does not have to travel around the circuit. It can also be a direct route to another station.

The goal is to replace a specific waypoint or a station in train commands. If the train, after entering the real depot, could leave the depot without further defining the station or waypoint, it would be quite perfect.