Moderator: OpenTTD Developers
Just my two crazy cents.
I built a full adder and an 8-byte memory array.
Both use a train on a loop, timetabled, to deal with delays from gates changing status. All of the permanent memory has four inputs: DATA, RESET, WRITE, READ. If the WRITE bit is 0, no data can be written to the memory cell. If the READ bit is 0, all the outputs will be 0. If the RESET bit is 0, none of the bits in the cell can be changed to 1. Where DATA and WRITE are both 1, the memory becomes 1.
1 being a red light, 0 being green.
I can provide building templates if anyone is interested.
- Wuston Transport, 2nd Mar 2113.png
- A view of the memory array controller and about 4 cells. The memory cell that is part of the controller is the write buffer.
- (169.39 KiB) Downloaded 602 times
- Wuston Transport, 3rd Dec 2113.png
- A view of the string of full adders. Visible are eight full adders tied together (cout to cin), and the two memory cells it adds together. Also visible is the testing/assembly area for copy/pasting parts together, so there's some junk in the image.
- (73.51 KiB) Downloaded 550 times
Official TT-Jewel Staite FanClub
First is a single memory cell, a "bit cell". It's unpopulated (as is the third image), but it should have two Pegasus + Pax Carriages in the NOT gate and a single Chimaera in the loop after the NOT gate.
Second, a linked "nibble cell" (half byte). Notice the tunnels linking all of the READ, WRITE, RESET bits together for the block.
Third, the top portion (starting with bit 128, then 64, 32, etc. from left to right) of a "byte cell". This one is part of the 8-byte memory array, since I didn't have any stepped (notice that each one is a offset a tile from the next, so they sort of slant) bytes sitting around bare, so I took a shot of that one.
- Wuston Transport, 22nd Apr 2116.png
- A "bit" of memory. No tunnels in this cell (aside from the RESET one), but the inputs are all neatly labelled.
- (71.74 KiB) Downloaded 465 times
- Wuston Transport, 8th Apr 2116.png
- Four bits of memory, four cells. These are populated, and you can see the Chimaeras resting in the "0" or "false" position. There's a Chimaera head peeking out of a tunnel along the RESET line, keeping it red in place of a NOT gate.
- (113.6 KiB) Downloaded 410 times
- Wuston Transport, 8th Jun 2116.png
- A chunk of a byte of memory. Not populated. Notice that the tunnels have to step with the memory cells.
You can see DATA inputs coming in from the lower left on bridges, along with the RESET line (which has a NOT gate on the other end of its bridge).
- (127.19 KiB) Downloaded 438 times
Official TT-Jewel Staite FanClub
But then i saw the amazing LED counter and Osais gate designs.
So, by using Osais gates i started working on a ALU, and now it's done:
A 16 bit ALU with the numbers A and B (in two's complement) as input. It can perform the following operations:
- NOT A
- NOT B
- A AND B
- A OR B
The next stage is to make som registers and instruction decoding .
Good job Graschnikov
Could somebody rent me a piece of Russia? I want to build a working pentium 4 copy with real trains and try to boot windows XP with the help of 2 friends
An idea, how about a calculator which allows simple sums to be done by sending trains from 3 depots. The sum is length of train A in cars (/*+-) length of train C in cars
Where /*+- is decided by the length of train B (1-4 cars)
(Or replace cars with tiles)
So to do 4+5, I'd send out a 4 car train on track one, a 3 car on track 2 and a 5 car on track 3.
Or better, a modified z80 compatable with the Game Boy. Running Z4 on TTD at a speed of a few billionths original would just be too awesome for words
Watch the image... i hope that you enjoy it
ct in lets the train move up 1 signal, this make it possible for the train to switch around 0 an 1
When the train is changing from 1 to 0, its hits the ct out (connect it first with a not gate before you can use it as a ct in)
edit: its bether that you use not 1 as 0 cause this will respons faster...
the timing is not always good, you need it to improved by yourself
- new counter.PNG (34.71 KiB) Viewed 4880 times
Do you know a smarter moment then discovering that you where doing something wrong?
wtb greater mapsizes so you can have a 1k x 1k map with the ALU and the connections and another part of the map for the normal (but self regulated) network. And we need a special "logic gate trainset" with a inf speed and asceleration train.
Using logic gates for simple things like the contruction of a load balancer e.g. is pretty handy btw.
I just downloaded your self-regulating network and am very impressed. My digital skills are a bit lacking, so I was wondering if you could help me in figuring out that network of yours. It would be awesome if you could correct my misunderstandings as I try to explore the circuit.
1) At each coal mine there is an extra loop. The purpose of the train in this loop is to collect and store a full load of coal then deliver that load back. While it is in this part of the process, a train is forced to wait by a signal. Thus a waiting train will always have a full load ready.
2) At the last coal mine of the circuit is a couple interesting features. First is an overflow lane. The opening to this overflow lane is connected to a NOT gate. This NOT gates input is an OR gate whose inputs are the two slots for waiting trains. So if both slots are full then the OR gate will be 0 and the NOT gate will output 1. Since the Combo-signal for the bypass lane is connected to this NOT gate, then it will open. Since the waiting lane would be closed because of physical circumstance, the train simply goes through the overflow. I also noticed a signal track going back to another set of logic gates near the power plant. For discussion, I will call this the Overflow Flag.
3) After exiting the powerplant, the track has a short two-part branch. The first branch is the Flow Branch, which is chosen by default by passing trains. Attached to the entrance is a conditional gate that goes into an OR gate. This OR gate gets input from the Overflow Flag and a NOT gate attached to the second branch. The second branch is the Depot Branch, which is chosen only when the conditional gate on the Flow Branch is red. At its entrance is a train indicator that is connected to a NOT gate. Since this entrance is usually open, the NOT gate is usually red. This means that in most circumstances the only condition necessary for the Flow Branch to be cut off(in effect, forcing a train into the Depot Branch) is when the Overflow Flag is tripped. The only purpose of the train indicator==>NOT gate is to keep too many trains from accidentally going into the Depot Lane during unlucky timing.
4) The mechanism that controls train release is a conditional gate attached to a train on a loop. Once this train leaves its station, the gate is opened until the train returns around the loop. What confuses me is why the train ever leaves its station. This same logic structure is also attached as a third condition for the Flow Branch gate and the Overflow Lane gate.
A logic trainset is an essential addition now. Would be perfect for ECS, since production can fluctuate so easily. Also maybe an entire 'logic railset' could be developed. These rails would be build-able on water, so more land space could be devoted to actual rail. At least the trains should be super fast and super accel with 1HP.
Will trains stop in a station they are passing if they have no orders and auto-load? If that was true, then you could add an additional NOT gate to each mine which closes off the loop unless the queue was full. At that point train orders wouldn't be necessary and the only possible system problem would not having enough trains to deal with material production.
The OR gate goes well, because it doesn't need a train. The NOT and AND gate however are the weak points. I tried to make the other gates without using trains but this cant be done. But every single gate can be made as a combination of others(to be precise NAND and NOR wich is a combination of OR and NOT) . for example AND=
.............|---OR--NOT--- (don't mind the dots, they're only there because of the layout)
I was wondering if somebody could make a patch for a NOT traffic light. Or if the NAND gate (that already has been made in the past) could be updated so it works (I couldn't get it to work on r13911). It would make it possible to make an adder with less than half the size of a halfadder, which now are pretty big components to fit in on your map.
That way we don't need another trainset with infinite speed and accelaration(because there would ride no trains in the gates) and it would make the circuits a lot smaller and more importantly: faster.
The slowest part then would be the memory, but with a good design this also can probably be sped up to just a few seconds (or less).
This was my first post, I hope my idea can add something to this community!!
Or, wait. I see the headline of a newspaper in some years. "AMD sponsored 5 million USD for the development crew of OpenTTD". Somewhere in the text it says, AMD uses OpenTTD to plan the layout of future CPUs
Users browsing this forum: No registered users and 5 guests